EP610DC-15 vs EP610IDC-15 比較
詳細な並列比較: EP610DC-15 メーカー: Altera および EP610IDC-15 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610DC-15 | EP610IDC-15 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.95 | $9.95 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 15 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| 動作温度 | 0C to 70C (commercial) | 0C to +70C (commercial) |
| パッケージ | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CerDIP (ceramic DIP) |
| 実装タイプ | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |