EP610DC-20 vs EP610DC-25 比較
詳細な並列比較: EP610DC-20 メーカー: Intel および EP610DC-25 メーカー: Rochester Electronics。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 生産中仕様比較
| パラメータ | EP610DC-20 | EP610DC-25 |
|---|---|---|
| ブランド | Intel | Rochester Electronics |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.85 | $9.95 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EP610 | Altera Classic EPLD |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | — |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| 動作温度 | 0 °C to 70 °C (commercial) | 0 C to +70 C |
| パッケージ | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP, through-hole) |
| Programming Method | UV erasure + parallel programmer | JEDEC fuse-map / UV-erase |
| Process Technology | CMOS, UV-erasable floating gate | — |
| 実装タイプ | Through-hole | Through Hole |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |