EP610IDC-10 vs EP610DC-15 比較
詳細な並列比較: EP610IDC-10 メーカー: Intel および EP610DC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610IDC-10 | EP610DC-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.85 | $7.95 |
| Device Family | Altera Classic EPLD | — |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | 20 |
| I/O Pins | 20 | — |
| 動作温度範囲 | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: RoHS status] |
| 実装タイプ | Through-hole | Through-Hole |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Propagation Delay (tPD) | — | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| 動作温度 | — | 0C to 70C (commercial) |
| パッケージ | — | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | — | JEDEC fuse map, UV erasure |