EP610ILC-25 vs EP610DC-35 比較
詳細な並列比較: EP610ILC-25 メーカー: Altera および EP610DC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610ILC-25 | EP610DC-35 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $18.40 |
| Family | Classic EPLD (EP610 series) | Altera Classic EP610 |
| Device Type | EEPLD (Electrically Erasable PLD) | CPLD - Classic EPLD |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| 動作温度範囲 | 0 C to +70 C (commercial) | — |
| パッケージ | 28-pin PLCC (J-lead) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 実装タイプ | Surface Mount | Through-Hole (DIP) |
| Process Technology | CMOS, electrically erasable | CMOS |
| Programming Method | In-system, electrically erasable | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| 動作温度 | — | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |