EP610ILC-25 vs EP610IPC-25 比較
詳細な並列比較: EP610ILC-25 メーカー: Altera および EP610IPC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610ILC-25 | EP610IPC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $8.85 |
| Family | Classic EPLD (EP610 series) | Classic EPLD (EP610) |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | — |
| Product Terms | 160 | 160 |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| 動作温度範囲 | 0 C to +70 C (commercial) | — |
| パッケージ | 28-pin PLCC (J-lead) | 24-pin PDIP (Plastic DIP) |
| 実装タイプ | Surface Mount | Through-Hole |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb, PDIP package) |
| Architecture | — | PAL-type, CMOS, Erasable |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| 動作温度 | — | 0 °C to +70 °C (Commercial) |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| MSLレベル | — | [DATA_NEEDED: MSL level] |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |