EP610IPC-25 vs EP610PC-25T 比較
詳細な並列比較: EP610IPC-25 メーカー: Intel および EP610PC-25T メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ ラストタイムバイ仕様比較
| パラメータ | EP610IPC-25 | EP610PC-25T |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.85 | $28.95 |
| Family | Classic EPLD (EP610) | — |
| Architecture | PAL-type, CMOS, Erasable | — |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | — |
| 動作温度 | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (commercial) |
| パッケージ | 24-pin PDIP (Plastic DIP) | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | — |
| TTL Compatibility | 100% TTL emulation | — |
| 実装タイプ | Through-Hole | Through-hole |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | Non-compliant (contains Pb, PDIP package) | [DATA_NEEDED: RoHS status] |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | 300 usable gates |
| Manufacturer | — | Intel (formerly Altera) |
| Distributor / Stocking Source | — | Rochester Electronics, LLC |
| Device Family | — | Altera Classic EPLD - EP610 |
| Device Type | — | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Macro Cells | — | 16 |
| Registers | — | 16 |
| User I/Os | — | 16 |
| Propagation Delay (tPD) | — | 25 ns (speed grade 25) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fmax] |
| Pipelined Data Rate | — | up to 100 MHz |
| Process Technology | — | ECMOS (CMOS, EPROM-based) |
| Pinout Compatibility | — | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Programming Method | — | OTP (one-time programmable) via Altera programming hardware |
| Shipping Form (T suffix) | — | Tube |