EP610PC-20T vs EP910PC-20T 比較

詳細な並列比較: EP610PC-20T メーカー: Intel および EP910PC-20T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP610PC-20T EP910PC-20T
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND Unknown
在庫状況 In Stock In Stock
単価(USD) $7.20 $8.70
Family Classic EPLD Classic EPLD
Logic Elements / Macrocells 16 macrocells —
Usable Gates 300 gates —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fMAX) 62.5 MHz —
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V —
Number of Dedicated Inputs 16 —
Number of I/O Pins 16 —
Programmable Output Enable Yes (per macrocell) —
パッケージ 24-pin PDIP (Plastic DIP) —
実装タイプ Through-Hole —
動作温度 0C to +70C (Commercial) [DATA_NEEDED: operating temperature range]
Programming Technology UV-erasable EPROM, CMOS —
Development Tool MAX+PLUS II —
RoHS ステータス unknown unknown
Device Type — EPLD
Fabrication Technology — CMOS
Logic Integration — 300 to 900 usable gates
Logic Emulation — 100% TTL emulation
Application Function — High-speed, low-power logic integration
Programmable Device Class — Erasable programmable logic device
Device Family — Altera Classic EPLD Family
Speed Grade — 20 ns
Package Code — PC
Package Pin Count — [DATA_NEEDED: package pin count]
Package Dimensions — [DATA_NEEDED: package dimensions]
電源電圧 — [DATA_NEEDED: operating supply voltage]
I/O Count — [DATA_NEEDED: I/O count]
Internal Logic Capacity — 300 to 900 usable gates
Supported Logic Integration — Multiple PAL- and GAL-type devices
Programming Interface — [DATA_NEEDED: programming interface]
Programming Voltage — [DATA_NEEDED: programming voltage]
Mounting Technology — [DATA_NEEDED: mounting technology]
REACH Status — unknown
AEC-Q100 Qualification — not_applicable
Lead-Free Status — unknown
Halogen-Free Status — unknown

データシート&リソース

すべての製品を閲覧 BOMを作成 見積もり依頼