EP910IPC-15 vs EP910PI-15T 比較
詳細な並列比較: EP910IPC-15 メーカー: Altera および EP910PI-15T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IPC-15 | EP910PI-15T |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.95 | $10.95 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 15 ns max (speed grade -15) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 動作温度 | 0C to +70C (commercial, IPC suffix) | [DATA_NEEDED: industrial/commercial temp range] |
| パッケージ | PDIP-40 (Plastic DIP, 40-pin) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| 実装タイプ | Through-Hole | Through-Hole |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| ピン数 | 40 | — |
| RoHS ステータス | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Family | — | Altera Classic EPLD (EP910 series) |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| 電源電圧 | — | 4.5 V to 5.5 V (5 V nominal) |
| Technology | — | CMOS EEPROM (electrically erasable) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | — | JEDEC-standard, serial/parallel programmer |