EP910IPC-25 vs EP910LC-30Y 比較
詳細な並列比較: EP910IPC-25 メーカー: Intel および EP910LC-30Y メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IPC-25 | EP910LC-30Y |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $25.40 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | — |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | — |
| 動作温度 | 0C to +70C (commercial grade) | Commercial 0C to +70C |
| パッケージ | 40-pin PDIP (PDIP-40) | PLCC-44 |
| 実装タイプ | Through-Hole | Surface Mount (PLCC socket) |
| Programming Method | EPROM cell (OTP / UV erasable) | — |
| Development Tool | MAX+PLUS II | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Counter Frequency (fMAX) | — | 100 MHz (family maximum) |
| 電源電圧 | — | 5 V (TTL-compatible) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Speed/Power Grade | — | LC (low-power, 30ns) |
| Processing Flow | — | Y (extended reliability) |
| Logic Compatibility | — | 100% TTL emulation |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status not specified in retrieved data] |