EP910LC-35 vs EP910LC-25 比較
詳細な並列比較: EP910LC-35 メーカー: Altera および EP910LC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LC-35 | EP910LC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.75 | $2.20 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM | CMOS (EPROM-based) |
| パッケージ | PLCC-44 (J-lead, LC suffix) | 28-pin PLCC (LC suffix) |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| ピン数 | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | — |
| RoHS ステータス | Not applicable (legacy product) | [DATA_NEEDED: RoHS status] |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| Dedicated Inputs | — | 16 |
| 実装タイプ | — | Surface Mount |
| Operating Voltage | — | [DATA_NEEDED: VCC range] |
| Programmable | — | Yes (EPROM, UV-erasable on windowed variants) |
| I/O Pins | — | [DATA_NEEDED: I/O count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |