EP910LC-40T vs EP910LI-40T 比較
詳細な並列比較: EP910LC-40T メーカー: Altera および EP910LI-40T メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LC-40T | EP910LI-40T |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $9.75 |
| Family | Altera Classic EPLD | Classic EPLD |
| Equivalent Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 4 Logic Expandable AND-OR arrays | — |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Maximum Frequency (fMAX) | 25 MHz | — |
| 電源電圧 | 5 V (4.75 V to 5.25 V) | 5 V (typical) |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable EPROM |
| パッケージ | PLCC-44 (PQCC44) | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC |
| 動作温度 | -40 C to +85 C (commercial, per -LC suffix family) | -40C to +85C (Industrial) |
| Programming | Altera MAX+PLUS II / APLUS tools | — |
| Erase/Reprogram Cycles | 100 (windowed UV-erase family) | — |
| ピン数 | 44 | — |
| Packaging Option | Tape and Reel (T suffix) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - not stated in web data] | [DATA_NEEDED: rohs status] |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Product Terms | — | 240 |
| Architecture | — | PAL-type with global bus |
| Programming Method | — | Altera Master Programming Unit (MPU), no JTAG |