EP910LC44 vs EP910LI-35BF 比較

詳細な並列比較: EP910LC44 メーカー: Altera および EP910LI-35BF メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

Altera
EP910LC44 EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera

EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera

EP910LC44 ⚠ ラストタイムバイ

仕様比較

パラメータ EP910LC44 EP910LI-35BF
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 ラストバイ Obsolete
在庫状況 In Stock In Stock
単価(USD) $8.95 $23.95
Product Family Classic EPLD (EP910 Series) —
Manufacturer Altera Corporation (now Intel PSG) —
Device Type Erasable Programmable Logic Device (EPLD) —
Macrocells 24 24
Total Product Terms 240 —
Dedicated Inputs 12 —
I/O Pins 24 —
Total Input Pins 36 (12 dedicated + 24 I/O as inputs) —
Global Clock Inputs 2 —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal)
Propagation Delay (LC grade) [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] —
Propagation Delay (LC-30 grade) 33 ns (per EP910LC44-30 verified data) —
Process Technology CMOS —
パッケージ 44-pin PLCC (J-leaded) 44-pin PLCC (J-lead)
動作温度 [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] —
Programming Method EPROM (erasable UV for ceramic; OTP for plastic PLCC) EPROM/UV-erase programmer (Altera Classic algorithm)
Architecture AND-OR sum-of-products with programmable macrocell feedback —
Logic Compatibility TTL-compatible CMOS I/O —
RoHS ステータス [DATA_NEEDED: not stated in verified data] —
Device Family — Altera Classic EPLD
Part Number Base — EP910
Logic Density — 450 usable gates
Maximum Pin-to-Pin Delay (tpd) — 35 ns
Maximum Toggle Frequency (fmax) — 28.6 MHz
動作温度範囲 — Industrial (LI suffix)
Technology — CMOS, UV-erasable
Output Polarity Control — Programmable XOR per macrocell
Flip-Flop Type — Selectable D/T/JK/SR per macrocell
TTL Compatibility — 100% TTL emulation
Compliance / EOL Status — Obsolete - last-time buy exhausted; second-source via Rochester Electronics

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