EP910LI-12 vs EP910LI-50 比較
詳細な並列比較: EP910LI-12 メーカー: Altera および EP910LI-50 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LI-12 | EP910LI-50 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.95 | $65.00 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Propagation Delay (tPD) | 12 ns | 50 ns |
| Maximum Frequency (fMAX) | 76.9 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V typical) | 5 V +/- 10% |
| I/O Pins | 24 | [DATA_NEEDED: I/O pin count] |
| Inputs (with input registers) | 36 | — |
| パッケージ | 28-PLCC (windowed ceramic, J-Lead) | — |
| 動作温度 | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Process Technology | 1.0-micron CMOS EPROM | — |
| Power Dissipation (typical) | 200 mW at 5 V | — |
| Programming Method | UV-erasable via windowed package | EPROM programmer (UV-erasable window) |
| Logic Compatibility | TTL-compatible I/O | — |
| RoHS ステータス | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Family | — | Altera Classic EPLD |
| Package Type | — | CERDIP-40 (L) |
| Package Pin Count | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Logic Blocks | — | Classic AND/OR array architecture |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |