EP910LI-30 vs EP910LC-30 比較
詳細な並列比較: EP910LI-30 メーカー: Rochester Electronics および EP910LC-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete
仕様比較
| パラメータ | EP910LI-30 | EP910LC-30 |
|---|---|---|
| ブランド | Rochester Electronics | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $49.50 | $22.50 |
| Family | Altera Classic EPLD EP910 | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 | — |
| Equivalent Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | 30 ns (max) |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) | 5 V (nominal, TTL) |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | — |
| 動作温度 | -40C to +85C (Industrial) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS (EPROM-based) |
| パッケージ | 44-pin PQCC / PLCC-44 (J-lead) | — |
| 実装タイプ | Surface Mount (socket recommended for UV erasure) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 22 | — |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance not verified in scraped data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | — |
| Macrocell Count | — | 24 |
| Maximum Toggle Frequency | — | 62 MHz |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| MSLレベル | — | [DATA_NEEDED: MSL level] |