EP910LI-40 vs EP910LI-50 比較
詳細な並列比較: EP910LI-40 メーカー: Altera および EP910LI-50 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LI-40 | EP910LI-50 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $12.90 | $65.00 |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 bidirectional | [DATA_NEEDED: I/O pin count] |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 50 ns |
| Technology | Low-power CMOS (L-suffix) | CMOS, UV-erasable EPROM |
| 動作温度 | -40C to +85C (industrial, I-suffix) | -40C to +85C (industrial) |
| パッケージ | PLCC-44 (J-lead, windowed ceramic) | — |
| 実装タイプ | Surface Mount (socket-compatible) | — |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| RoHS ステータス | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 450 |
| Package Type | — | CERDIP-40 (L) |
| Package Pin Count | — | 40 |
| Supply Voltage (VCC) | — | 5 V +/- 10% |
| Logic Blocks | — | Classic AND/OR array architecture |
| Programming Method | — | EPROM programmer (UV-erasable window) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |