EP910LI44 vs EP910LI-40 比較
詳細な並列比較: EP910LI44 メーカー: Altera および EP910LI-40 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LI44 | EP910LI-40 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.20 | $12.90 |
| Family | Classic EPLD | — |
| Architecture | PAL-type, CMOS, One-Time-Programmable | — |
| Macrocells | 24 | 24 |
| Package Type | PLCC-44 (J-lead, surface mount) | — |
| Total Pins | 44 | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O | 24 | — |
| Maximum Logic Inputs | 36 | 36 |
| Maximum Outputs | 24 | — |
| Flip-Flops | 24 | — |
| External Clocks | 2 | — |
| Maximum Propagation Delay | [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) | — |
| Operating Temperature (L grade) | -40 °C to +85 °C (industrial) | — |
| Technology | CMOS | Low-power CMOS (L-suffix) |
| Programmability | UV-erasable (windowed) or OTP | UV-erasable, JEDEC-standard algorithm |
| RoHS ステータス | non-compliant (original PLCC-44 lead finish) | Non-compliant (windowed ceramic PLCC, legacy) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount (socket-compatible) |
| Programming Method | Altera Logic Programmer card / Data I/O / third-party EPROM programmers | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| I/O Pins | — | 24 bidirectional |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| 動作温度 | — | -40C to +85C (industrial, I-suffix) |
| パッケージ | — | PLCC-44 (J-lead, windowed ceramic) |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |