EPC144ILC20 vs EPC1441LI20 比較
詳細な並列比較: EPC144ILC20 メーカー: Intel および EPC1441LI20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC144ILC20 | EPC1441LI20 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | Memory ICs | Memory ICs |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $8.10 |
| Manufacturer | Altera (now Intel) | — |
| Part Family | EPC144 - Configuration EPROM | — |
| メモリタイプ | OTP CMOS Configuration EPROM (UV-erasable, factory OTP-programmed) | OTP Configuration PROM (PROM) |
| メモリサイズ | 440,800 bit (54 KB) | — |
| インターフェース | Serial (Altera FLEX/MAX configuration - DCLK / DATA0 / nCONFIG / nSTATUS) | — |
| Supply Voltage VCC | 5 V (nominal) | — |
| パッケージ | PLCC-20 (Plastic Leaded Chip Carrier, JEDEC MS-018) | 20-pin PLCC (J-lead, 9x9 mm) |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | — |
| Configuration Mode | Master Serial / daisy-chain JTAG-style | — |
| Programmability | One-Time-Programmable (factory programmed by Altera with user bitstream) | — |
| JTAG Support | Yes (TDI/TDO pins for ByteBlasterMV / USB-Blaster ISP) | — |
| Compatible FPGAs | Altera EPF8282, EPF8452, EPF10K-series Classic FPGAs | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| 実装タイプ | Surface Mount (PLCC-20 socket or SMT land pattern) | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Configuration Interface | — | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| 電源電圧 | — | 3.3 V |
| 動作温度 | — | -40 C to +85 C (industrial) |
| Pin Pitch | — | 1.27 mm |
| Programming Method | — | One-Time-Programmable via Altera programming hardware |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |