EPC2C20 vs EPC2L20N 比較
詳細な並列比較: EPC2C20 メーカー: Altera および EPC2L20N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2C20 | EPC2L20N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $17.20 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| パッケージ | [DATA_NEEDED: package] | — |
| ピン数 | [DATA_NEEDED: pin count] | 20 |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| 機能 | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| メモリサイズ | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| パッケージ / ケース | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| 動作温度 | — | 0C to +70C (commercial) |
| Supported FPGA Families | — | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | — | Yes (multi-PROM chain via CE control) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| 実装タイプ | — | Surface Mount (J-Lead PLCC) |
| Lead Finish | — | Matte Tin (Pb-free) |
| MSLレベル | — | 3 (168 hours) |