EPC2LI20N vs EPC2LC20 比較
詳細な並列比較: EPC2LI20N メーカー: Altera および EPC2LC20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2LI20N | EPC2LC20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | Memory ICs | Memory ICs |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.10 | $7.20 |
| メモリタイプ | Non-volatile configuration PROM (Flash) | Non-volatile configuration PROM |
| メモリサイズ | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Configuration Mode | Serial | — |
| Maximum Configuration Frequency | 10 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V | — |
| パッケージ / ケース | 20-PLCC (J-Lead), 9x9 mm | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Packaging | Tube | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Supported FPGA Series | ACEX 1K, APEX II, Cyclone, Stratix II | — |
| JTAG Interface | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) | — |
| Configuration Pins | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Non-Compliant (original Altera Pb-containing part) |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| パッケージ | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |