EPC2LS20U vs EPC2T132N 比較
詳細な並列比較: EPC2LS20U メーカー: Altera および EPC2T132N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2LS20U | EPC2T132N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | Memory ICs | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $4.25 | $17.80 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| インターフェース | Altera serial configuration / JTAG | Altera serial configuration (4-wire JTAG for ISP) |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| パッケージ | 20-PLCC (J-lead, 9x9 mm) | TQFP-32 (T132) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| 動作温度 | [DATA_NEEDED: Operating Temperature] | -40C to +85C (industrial) |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| MSLレベル | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL level] |
| Compliance | RoHS (Pb-free per U suffix) | — |
| メモリタイプ | — | Flash (NOR, serial configuration) |
| Memory Capacity | — | 1.6 Mbit (2 Mbit raw, 1.6 Mbit usable) |
| Serial Clock Frequency | — | 10 MHz maximum |
| 電源電圧 | — | 3.0 V to 3.6 V |
| 実装タイプ | — | Surface Mount |
| Program/Erase Endurance | — | 100,000 cycles per sector |
| Data Retention | — | 20 years minimum |
| In-System Programmable | — | Yes (IEEE 1149.1 JTAG) |
| Configuration Compatibility | — | APEX II, APEX 20K, ACEX 1K, FLEX 10K/10KE/6000, Cyclone, Stratix, Mercury |
| Multi-Device Daisy Chain | — | Yes (supported) |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |