EPC80C100T vs EPC80C100 比較

詳細な並列比較: EPC80C100T メーカー: Intel および EPC80C100 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPC80C100T EPC80C100
ブランド Intel Intel
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND NRND
在庫状況 In Stock In Stock
単価(USD) $25.40 $24.10
Product Type Enhanced Configuration Device for SRAM-based LUT FPGAs —
Manufacturer Intel (formerly Altera) —
Family Enhanced Configuration (EPC) Devices —
Memory Density [DATA_NEEDED: density in Mbit] —
電源電圧 3.0 V to 3.6 V (3.3 V typical) —
Configuration Modes FPP, PPS, PPA, PS, JTAG —
JTAG Interface IEEE 1149.1 in-system programming —
Internal Oscillator 50 MHz —
Multi-Boot Pages Up to 8 configuration pages —
Page-Mode Read Supported —
In-System Programmability Yes (continuous, via JTAG) —
パッケージ 100-pin PQFP (T = tape and reel) 100-pin PQFP / EQFP
Compatible FPGA Families APEX 20K, APEX II, Mercury, ACEX 1K, Cyclone, Stratix —
動作温度 -40C to +85C (industrial, [DATA_NEEDED: confirm grade]) -40C to +85C (industrial)
RoHS ステータス [DATA_NEEDED: verify from manufacturer page] Compliant (Pb-free EQFP)
Lead-Free [DATA_NEEDED: verify from manufacturer page] —
Device Type — Enhanced Configuration (EPC) Memory
Configuration Memory Size — 80 Mbit
Target FPGA Families — Cyclone, Cyclone II, Stratix, APEX 20K, ACEX 1K
Configuration Modes Supported — Passive Serial (PS), Passive Parallel Synchronous (PPS), JTAG
Cascading Support — Yes (multi-device daisy chain)
In-System Programming — IEEE 1532 / JTAG
Core Supply Voltage — 3.3 V
I/O Supply Voltage — 3.3 V (5 V tolerant inputs on some revisions)
Programming Interface — JTAG (IEEE 1149.1) boundary scan
実装タイプ — Surface Mount
Page-mode Configuration — Supported
Compression Support — Altera proprietary bitstream compression
MSLレベル — 3 (168 hours)
Modern Replacement Family — EPCS / EPCQ serial flash + Altera generic flash loader

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