EPF10K100EFC484-2 vs EPF10K130EFC484-2N 比較
詳細な並列比較: EPF10K100EFC484-2 メーカー: Altera および EPF10K130EFC484-2N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPF10K100EFC484-2 | EPF10K130EFC484-2N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $185.40 | $799.00 |
| Series | FLEX-10KE | FLEX-10KE |
| Manufacturer | Altera (Intel) | — |
| Family | FLEX-10KE | — |
| Logic Elements / Cells | 49,992 | — |
| Logic Array Blocks (LABs) | 624 | — |
| Total RAM Bits | [DATA_NEEDED: total embedded memory bits] | — |
| Number of I/O | 338 | — |
| Supply Voltage (Core) | 2.375 V to 2.625 V | — |
| 実装タイプ | Surface Mount | — |
| 動作温度 | 0C to +70C (commercial) | 0 °C to 70 °C |
| パッケージ / ケース | 484-BBGA | — |
| Supplier Device Package | 484-FBGA (23x23 mm) | — |
| Speed Grade | -2 | — |
| Process Technology | 0.22 um SRAM CMOS | 0.22 µm |
| Configuration Method | SRAM - serial JTAG or EPC configuration device | — |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI, SSTL | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Gate Count | — | 130,000 gates |
| Logic Cells | — | 6,656 cells |
| Logic Family | — | CMOS |
| Listed Maximum Frequency | — | 333.33 MHz |
| Propagation Delay | — | 0.6000 ns |
| User I/Os | — | 369 I/Os |
| Alternative I/O Count Listing | — | 274 I/Os |
| Embedded Memory | — | 65,536 bits |
| Logic Array Blocks | — | 832 LABs |
| 電源電圧 | — | 2.5 V nominal |
| Verified Supply-Voltage Range | — | 2.375 V to 2.625 V |
| Alternate Supply Listing | — | 3.3 V |
| パッケージ | — | 484-ball FBGA, 23 mm × 23 mm |
| Package Pin Count | — | 356 pins |
| Ball Pitch | — | 1 mm |
| RoHS Compliance | — | unknown |
| REACH Compliance | — | unknown |
| AEC-Q100 Qualification | — | unknown |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |