EPF10K50SQC240-1N vs EPF10K50SQC240-3N 比較
詳細な並列比較: EPF10K50SQC240-1N メーカー: Intel および EPF10K50SQC240-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPF10K50SQC240-3N - FLEX 10KE 50K Gates FPGA, 240-PQFP | Altera / Intel
EPF10K50SQC240-3N Obsolete仕様比較
| パラメータ | EPF10K50SQC240-1N | EPF10K50SQC240-3N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $67.50 | $60.00 |
| Family | FLEX 10KS | FLEX 10KE |
| Series | FLEX-10KS | — |
| Logic Elements / Cells | 2,880 | — |
| Typical Gates | 50,000 | 50,000 |
| System Gates | 40,960 | 40,960 |
| Number of LABs | 360 | — |
| Number of EABs | [DATA_NEEDED: EAB count] | — |
| User I/Os | 189 | 189 (per DigiKey listing); 274 user I/Os (per Digchip listing) |
| Supply Voltage (Core) | 2.375 V to 2.625 V | — |
| Process Technology | 0.22 micrometer CMOS | 0.22 µm CMOS |
| Internal Frequency (max) | 250 MHz | — |
| Propagation Delay | [DATA_NEEDED: ns value for -1 speed grade] | — |
| 動作温度 | 0C to +70C (Commercial) | 0 °C to 70 °C (Commercial) |
| パッケージ | 240-PQFP / 240-BFQFP (32 x 32 mm) | 240-pin PQFP (Power Quad Flat Pack), 34.60 x 34.6 mm, 0.5 mm pitch |
| 実装タイプ | Surface Mount | Surface Mount |
| Speed Grade | -1 | -3 (faster Fmax) |
| JTAG Support | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Rev. 2.2 (3.3V and 5.0V at 33/66 MHz) | — |
| RoHS ステータス | [DATA_NEEDED: from manufacturer] | Compliant (Pb-free N suffix) |
| Configuration Method | Serial EPROM (EPC2/EPC8) or ByteBlaster | — |
| Logic Family | — | CMOS |
| Logic Cells / Elements | — | 2,880 |
| Logic Array Blocks (LABs) | — | 360 |
| Embedded Array Blocks (EABs) | — | 12 |
| On-chip EAB Memory | — | 24 Kbits |
| Number of I/Os (per distributor) | — | 189 (DigiKey / Mouser) |
| Propagation Delay (tpd) | — | 0.6 ns |
| Internal Frequency (Fmax) | — | 166.67 MHz |
| Core Supply Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | MultiVolt: 2.5 V / 3.3 V / 5.0 V tolerant |
| Lead-Free Finish (N suffix) | — | Yes |
| JTAG Boundary Scan | — | IEEE Std. 1149.1 compliant |
| Programming Technology | — | SRAM-based, in-system reconfigurable via JTAG |
| Design Tool | — | Altera Quartus II (FLEX 10KE support) |