EPM1270F256C5 vs EPM1270F256I5N 比較
詳細な並列比較: EPM1270F256C5 メーカー: Altera および EPM1270F256I5N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM1270F256C5 | EPM1270F256I5N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $25.40 | $14.85 |
| Series | MAX II | MAX II |
| Family | EPM1270 | MAX II (EPM1270) |
| Macro Cells | 980 | 980 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Logic Delay (tPD) | 6.2 ns (C5 speed grade) | — |
| Internal Operating Frequency | 201.1 MHz | — |
| Core Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Standards Supported | LVCMOS/LVTTL 1.8 V, 2.5 V, 3.3 V, 5.0 V (MultiVolt) | — |
| Process Technology | 0.18 µm | 0.18-micron Flash-based CMOS |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | Non-volatile Flash (instant-on) |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Programming Interface | JTAG (IEEE 1149.1) / ISP via ByteBlaster / USB-Blaster | JTAG IEEE 1149.1 (boundary-scan + ISP) |
| パッケージ | 256-ball FineLine BGA (FBGA-256) | 256-ball FBGA (FineLine BGA), 17 x 17 mm |
| 動作温度 | 0 °C to +85 °C (commercial, 'C' grade) | -40C to +100C (TJ), industrial |
| RoHS ステータス | Compliant | Compliant |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Logic Elements | — | 1270 |
| User I/O Pins | — | 212 |
| Maximum Operating Frequency | — | 201.1 MHz |
| Pin-to-Pin Logic Delay | — | 6.2 ns (I5 speed grade) |
| External Supply Voltage | — | 2.5 V / 3.3 V |
| Internal Core Voltage | — | 1.8 V (on-chip regulator) |
| I/O Bank Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) + 3.3 V PCI-compliant bank |
| Speed Grade | — | I5 (industrial, 6.2 ns tPD) |
| 実装タイプ | — | Surface Mount (SMT, BGA) |
| ハロゲンフリー | — | Compliant (per GlobalSpec) |
| Country of Origin | — | Malaysia / Republic of Korea |