EPM240F100C5N vs EPM240GF100I5N 比較
詳細な並列比較: EPM240F100C5N メーカー: Intel および EPM240GF100I5N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM240F100C5N | EPM240GF100I5N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.20 | $7.90 |
| Device Family | MAX II | — |
| Logic Elements (LEs) | 240 | — |
| Macrocells | 192 | — |
| User I/O Pins (maximum) | 80 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fmax per datasheet] | — |
| Global Clock Networks | [DATA_NEEDED: count] | — |
| パッケージ | 100-ball FineLine BGA (FBGA-100) | 100-ball FBGA (FineLine BGA), 11 mm x 11 mm, 1.0 mm pitch |
| 動作温度範囲 | 0C to +85C (commercial) | — |
| Supply Voltage Core (VCCINT) | 3.3 V | — |
| I/O Bank Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) | — |
| Configuration Memory | Non-volatile flash (instant-on) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE 1149.1 / IEEE 1532 compliant |
| Programming Interface | JTAG / ByteBlasterMV | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount |
| RoHS ステータス | Compliant | — |
| Series | — | MAX II |
| Logic Elements / Blocks | — | 240 LE |
| Number of Macrocells | — | 192 |
| Maximum User I/O | — | 80 |
| Propagation Delay (tpd, max) | — | 4.7 ns |
| Programmable Type | — | In-System Programmable (ISP) |
| Non-Volatile Memory | — | On-chip flash configuration |
| Internal Supply Voltage | — | 1.71 V to 1.89 V (regulated on-chip) |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Operating Temperature (TJ) | — | -40 C to +100 C |
| Lead-Free / RoHS | — | Yes (lead-free, RoHS compliant) |
| Logic Family | — | CMOS |
| Vertical Migration Family | — | EPM240 / EPM570 / EPM1270 / EPM2210 in same-package footprint |