EPM240M100I5N vs EPM240M100C4N 比較
詳細な並列比較: EPM240M100I5N メーカー: Altera および EPM240M100C4N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM240M100I5N | EPM240M100C4N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.95 | $7.45 |
| Series | MAX II | MAX II |
| Family | MAX II CPLD | — |
| Macro Cells | 192 | 192 |
| Logic Elements | 240 | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Propagation Delay (tPD) | 4.7 ns | — |
| On-die Non-volatile Memory | 8 Kbits | — |
| Process Technology | 0.18 µm, 6-layer metal flash | — |
| Core Voltage | 2.5 V / 3.3 V | — |
| I/O Bank Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User I/O Pins | [DATA_NEEDED: user IO count for MBGA package] | — |
| パッケージ | 100-MBGA (Micro FineLine BGA) | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| 動作温度 | -40 °C to +100 °C (industrial) | -40 C to +125 C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| RoHS ステータス | Compliant | Lead Free (per DigiChip spec sheet) |
| Lead-Free | Yes | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Family | — | EPM240 |
| User I/Os | — | 80 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Configuration Memory | — | Non-volatile on-chip flash (instant-on) |
| Logic Family | — | CMOS |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |