EPM240T100C3N vs EPM240T100C5N 比較
詳細な並列比較: EPM240T100C3N メーカー: Altera および EPM240T100C5N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM240T100C3N | EPM240T100C5N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.05 | $4.65 |
| Series | MAX II | — |
| Device Family | MAX II CPLD (EPM240) | — |
| Logic Elements (LE) | 240 | — |
| Macrocells | 192 | — |
| User I/O Pins | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| パッケージ | 100-pin TQFP (14x14 mm) | 100-pin TQFP (T100), 14x14 mm |
| Configuration Memory | Internal Flash (non-volatile) | — |
| Pin-to-Pin Logic Delay (tPD) | 4.4 ns (typical) | — |
| Maximum Operating Frequency | 200 MHz (internal oscillator) | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| 動作温度 | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial, 'C' suffix) |
| Quiescent Current (typical) | 35 mA | — |
| RoHS ステータス | Compliant | Compliant (lead-free) |
| 実装タイプ | Surface Mount | Surface Mount |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| Equivalent Macrocells | — | 192 |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Process Technology | — | 0.18 µm, 6-layer-metal flash |