EPM3032ALC44-10N vs EPM3032ALC44-10 比較
詳細な並列比較: EPM3032ALC44-10N メーカー: Altera および EPM3032ALC44-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM3032ALC44-10 - MAX 3000A CPLD, 32 Macrocells, 10ns, 44-PLCC | Intel / Altera
EPM3032ALC44-10 Obsolete仕様比較
| パラメータ | EPM3032ALC44-10N | EPM3032ALC44-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.94 | $0.98 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 600 gates | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal fMAX | 103.1 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Yes, IEEE 1149.1 compliant | — |
| パッケージ | 44-pin PLCC (J-Lead, surface mount) | 44-pin PLCC (J-Lead) |
| 実装タイプ | Surface Mount | Surface Mount / Socket |
| 動作温度 | [DATA_NEEDED: industrial/commercial range] | 0C to +70C (commercial) |
| RoHS ステータス | [DATA_NEEDED: compliant or non-compliant] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 600 |
| Maximum User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| In-System Programming | — | Yes - JTAG (IEEE Std. 1149.1) |
| Concurrent ISP | — | Yes - IEEE Std. 1532 |
| Process Technology | — | CMOS EEPROM |