EPM3032ALC44-4 vs EPM3032A-TC44-10 比較
詳細な並列比較: EPM3032ALC44-4 メーカー: Altera および EPM3032A-TC44-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3032ALC44-4 | EPM3032A-TC44-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.10 | $7.45 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| User I/O Pins | 34 | 34 |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) | — |
| Usable Gates | 600 to 10,000 (MAX 3000A family range) | — |
| パッケージ | 44-pin PLCC (J-Lead) | TQFP-44 |
| 動作温度 | 0°C to +70°C (Commercial) | — |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability (ISP) | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Programming Interface | JTAG (ByteBlaster / MasterBlaster) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| 実装タイプ | Surface Mount (PLCC J-Lead) | Surface Mount |
| Logic Array Blocks | — | 2 |
| Logic Gates | — | 600 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 227.3 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 3.0 V to 3.6 V (typ. 3.3 V) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Output Enables | — | 6 |
| Configuration Memory | — | CMOS EEPROM (non-volatile) |
| Operating Temperature (Commercial) | — | 0 °C to +70 °C |
| Process Technology | — | CMOS EEPROM |