EPM3064ATC100-10 vs EPM3064ATI100-10N 比較
詳細な並列比較: EPM3064ATC100-10 メーカー: Altera および EPM3064ATI100-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 Nrnd仕様比較
| パラメータ | EPM3064ATC100-10 | EPM3064ATI100-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $2.85 | $9.80 |
| Family | MAX 3000A | MAX 3000A |
| Logic Gates | 1250 gates | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| User I/O Pins | 34 | — |
| パッケージ | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP (industrial) |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant | — |
| Global Clock Signals | 2 (with optional inversion) | — |
| Output Enable Signals | 6 or 10 pin- or logic-driven | — |
| Output Slew-Rate Control | Programmable | — |
| Operating Temperature Grade | Commercial | — |
| MultiVolt I/O Support | 1.5V / 1.8V / 2.5V / 3.3V interfaces | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | RoHS Non-Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Type | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM |
| Usable Gates | — | 1,250 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O | — | 66 |
| Supply Voltage (Core / I/O) | — | 3.3 V |
| Pin-to-Pin Delay (tPD) | — | 10 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz (counter) |
| 動作温度 | — | -40 C to +85 C (industrial) |
| JTAG (IEEE 1149.1) | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) |
| MultiVolt I/O | — | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing |
| Lead-Free Status | — | Contains Lead |