EPM3064ATC100-10 vs EPM3128ATC100-10 比較
詳細な並列比較: EPM3064ATC100-10 メーカー: Altera および EPM3128ATC100-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 NrndAltera
EPM3128ATC100-10 - MAX 3000A 128-Macrocell CPLD, 10ns TQFP-100 | Intel / Altera
EPM3128ATC100-10 Nrnd仕様比較
| パラメータ | EPM3064ATC100-10 | EPM3128ATC100-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $2.85 | $8.10 |
| Family | MAX 3000A | — |
| Logic Gates | 1250 gates | — |
| Macrocells | 64 | 128 |
| Logic Array Blocks | 2 | — |
| User I/O Pins | 34 | — |
| パッケージ | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant | — |
| Global Clock Signals | 2 (with optional inversion) | — |
| Output Enable Signals | 6 or 10 pin- or logic-driven | — |
| Output Slew-Rate Control | Programmable | — |
| Operating Temperature Grade | Commercial | — |
| MultiVolt I/O Support | 1.5V / 1.8V / 2.5V / 3.3V interfaces | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 80 |
| Usable Gates | — | 2500 |
| Counter Frequency | — | 227.3 MHz |
| I/O Voltage Tolerance | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| 実装タイプ | — | Surface Mount |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 compliant (JTAG) |
| PCI Compliance | — | PCI Local Bus Specification Rev 2.2 (selected speed grades) |
| Logic Family | — | CMOS |
| 動作温度 | — | 0 C to 70 C (commercial) |