EPM3064ATC44-7N vs EPM3064ATI44-10 比較
詳細な並列比較: EPM3064ATC44-7N メーカー: Altera および EPM3064ATI44-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3064ATC44-7N | EPM3064ATI44-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $2.30 | $7.65 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 64 | — |
| Logic Array Blocks | 2 | — |
| Usable Gates | 1,250 | — |
| User I/O Pins | 34 | — |
| ピン数 | 44 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Counter Frequency | 192.3 MHz (-7 grade) | 227.3 MHz |
| Supply Voltage (VCC) | 3.3 V | — |
| MultiVolt I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | IEEE Std. 1149.1 compliant |
| ISP Standard | IEEE Std. 1532 compliant | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | Built-in, JTAG-driven | — |
| パッケージ | 44-pin TQFP | TQFP-44 (10x10 mm, 0.8 mm pitch) |
| 動作温度 | 0°C to +85°C (commercial) | -40C to +85C (Industrial) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant | Non-Compliant (contains lead, per DigiChip listing) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Type | — | In-System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 64 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of Usable Gates | — | 1,250 |
| Number of User I/O Pins | — | 34 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant (MultiVolt I/O) |
| Lead Free Status | — | Contains Lead |
| Process Technology | — | CMOS, EEPROM |
| Programming Cycles | — | [DATA_NEEDED: typical program/erase endurance] |