EPM3256AQC208-10N vs EPM3512AQC208-3N 比較
詳細な並列比較: EPM3256AQC208-10N メーカー: Altera および EPM3512AQC208-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3256AQC208-10N | EPM3512AQC208-3N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $4.62 | $16.40 |
| Series | MAX 3000A | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements/Blocks | 16 LABs | — |
| Usable Gates | 10,000 | — |
| Number of I/O Pins | 161 (158 user I/O per Arrow listing) | — |
| Propagation Delay (tpd) | 10 ns (max) | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V (3.3 V typical) | — |
| 動作温度 | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| パッケージ / ケース | 208-BFQFP / 208-PQFP (28x28 mm) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| ISP Compliance | IEEE Std. 1532 | IEEE Std. 1532 |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| I/O Tolerance | 5 V tolerant, MultiVolt interface | — |
| RoHS ステータス | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] | [DATA_NEEDED: not stated in retrieved snippets] |
| Family | — | MAX 3000A |
| Macrocells | — | 512 |
| User I/O Pins | — | 172 |
| Logic Array Blocks (LABs) | — | 16 |
| Macrocells per LAB | — | 32 |
| Pin-to-Pin Logic Delay | — | 3 ns (speed grade -3) |
| Global Clock Setup Time | — | [DATA_NEEDED: actual tSU at 3 ns grade] |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) |
| パッケージ | — | PQFP-208 |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED] |