EPM3512AFC256-20 vs EPM3512AFC256-18 比較
詳細な並列比較: EPM3512AFC256-20 メーカー: Altera および EPM3512AFC256-18 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 ObsoleteAltera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 Obsolete仕様比較
| パラメータ | EPM3512AFC256-20 | EPM3512AFC256-18 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $17.20 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Typical Usable Gates | 10,000 | — |
| Speed Grade | -20 (20 ns tPD) | — |
| パッケージ | 256-ball FBGA (Fine-pitch BGA) | 256-ball FineLine BGA (FCBGA) |
| ピン数 | 256 | — |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| JTAG Support | Yes (boundary-scan + ISP) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial grade] |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not specified in retrieved data] |
| MSLレベル | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Configuration Memory | Internal EEPROM | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD1) | — | 18 ns |
| Global Clock Networks | — | 4 |
| VCCINT (Core Supply) | — | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | — | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | — | 1.0 mm |