EPM3512AFC256-7N vs EPM3512AFC256-2N 比較
詳細な並列比較: EPM3512AFC256-7N メーカー: Altera および EPM3512AFC256-2N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N Obsolete仕様比較
| パラメータ | EPM3512AFC256-7N | EPM3512AFC256-2N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $61.00 | $25.80 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| User I/Os | 208 | — |
| Logic Blocks | 16 (32 macrocells each) | — |
| Propagation Delay (tPD) | 7.5 ns | [DATA_NEEDED: tPD in ns] |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant I/O | Yes | — |
| In-System Programmability | IEEE Std. 1532 compliant | IEEE Std. 1532 JTAG |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Process Technology | CMOS EEPROM, 0.30 um | 0.30 µm CMOS EEPROM |
| パッケージ | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FineLine BGA (FC-256) |
| 動作温度 | 0 C to 70 C (commercial) | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Compliant |
| Logic Array Blocks (LABs) | — | 32 |
| Maximum User I/O Pins | — | 212 |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX in MHz] |
| Configuration Memory | — | Non-volatile EEPROM |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 2.5 V / 3.3 V / 5.0 V MultiVolt |
| PCI Compliance | — | 3.3 V PCI-compliant |
| Operating Temperature (Commercial) | — | 0 °C to +70 °C |
| Lead-Free | — | Yes |