EPM3512AFC256-7N vs EPM3512AFC256-3N 比較
詳細な並列比較: EPM3512AFC256-7N メーカー: Altera および EPM3512AFC256-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N Obsolete仕様比較
| パラメータ | EPM3512AFC256-7N | EPM3512AFC256-3N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $61.00 | $23.40 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 208 | — |
| Logic Blocks | 16 (32 macrocells each) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| 5V Tolerant I/O | Yes | — |
| In-System Programmability | IEEE Std. 1532 compliant | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP |
| Process Technology | CMOS EEPROM, 0.30 um | — |
| パッケージ | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FineLine BGA (FC-256) |
| 動作温度 | 0 C to 70 C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Operating Frequency | — | 116.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 3.5 ns (speed grade -3) |
| Speed Grade | — | -3 (slowest in family) |
| Configuration Memory | — | Non-volatile EEPROM |