EPM3512AFI256-7N vs EPM3512AFC256-10N 比較
詳細な並列比較: EPM3512AFI256-7N メーカー: Altera および EPM3512AFC256-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera
EPM3512AFI256-7N ⚠ ラストタイムバイ仕様比較
| パラメータ | EPM3512AFI256-7N | EPM3512AFC256-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.95 | $43.22 |
| Family | MAX 3000A | MAX 3000A |
| Device Logic Elements / Macrocells | 512 macrocells | — |
| Typical Usable Gates | 10,000 gates | — |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: number of LABs] |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Maximum Operating Frequency (fMAX) | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD, speed grade -7) | approximately 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Levels | 2.5 V / 3.3 V / 5 V mixed | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| パッケージ | 256-ball FBGA | 256-ball FBGA (17 mm x 17 mm) |
| 動作温度範囲 | -40C to +85C (industrial) | — |
| Lead-Free / RoHS | Yes ('N' suffix, lead-free) | — |
| Design Software | Quartus II (legacy MAX 3000A support) | — |
| Speed Grade | -7 | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| Macrocells | — | 512 |
| Usable Gates | — | 10000 |
| User I/O Pins | — | 208 |
| Operating Frequency (fMAX) | — | [DATA_NEEDED: fMAX MHz] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Setup Time (tSU) | — | 4.5 ns |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 3.3 V or 2.5 V |
| Technology | — | CMOS EEPROM-based, non-volatile |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| ISP Interface | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |