EPM3512AQC208-10 vs EPM3512AQC208-15N 比較
詳細な並列比較: EPM3512AQC208-10 メーカー: Altera および EPM3512AQC208-15N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC208-10 | EPM3512AQC208-15N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $22.10 | $20.50 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | — |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 32 | 16 |
| User I/Os | 208 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE Std. 1532) | Yes (IEEE Std. 1532 compliant) |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | — |
| パッケージ | 208-pin PQFP | PQFP-208 (QC208) |
| 動作温度 | 0C to +70 C (commercial) | 0C to +70C (commercial) |
| RoHS ステータス | [DATA_NEEDED: RoHS status not in verified data] | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macro Cells | — | 512 |
| Maximum User I/O Pins | — | 172 |
| Typical Usable Gates | — | 12,000 |
| Number of Logic Elements | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Operating Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V (MultiVolt) |
| Programmable I/O Standards | — | LVTTL, LVCMOS, PCI (with external resistor) |
| JTAG Support | — | Yes (BST/Boundary-Scan Test) |
| 実装タイプ | — | Surface Mount |