EPM3512AQC208-10N vs EPM3512AQC208-2 比較
詳細な並列比較: EPM3512AQC208-10N メーカー: Intel および EPM3512AQC208-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC208-10N | EPM3512AQC208-2 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $42.80 | $18.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | Up to 10,000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/Os | 172 | — |
| パッケージ | 208-pin PQFP (Plastic Quad Flat Pack) | PQFP-208 (QC) |
| 電源電圧 | 3.3 V | — |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz | — |
| Speed Grade | -10 | -2 |
| Process Technology | CMOS EEPROM | 0.30 µm EEPROM |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | — |
| 動作温度 | 0 C to 70 C (commercial) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status not in verified web data] | Non-compliant (legacy PQFP) |
| User I/O Pins | — | 172 |
| Supply Voltage (Core) | — | 3.3 V |
| Output Drive Voltage | — | 2.5 V / 3.3 V programmable |
| Input Voltage Tolerance | — | 2.5 V / 3.3 V / 5.0 V |
| Program/Erase Endurance | — | 100 cycles (typical) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| User I/O Banks | — | 4 |
| 動作温度範囲 | — | Commercial (0C to +70C) |
| 実装タイプ | — | Surface Mount |
| Lead-Free | — | No (SnPb lead finish) |
| Security Bit | — | Yes (programmable) |