EPM3512AQC208-15N vs EPM3512AQC208-10S 比較
詳細な並列比較: EPM3512AQC208-15N メーカー: Altera および EPM3512AQC208-10S メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC208-15N | EPM3512AQC208-10S |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $20.50 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Maximum User I/O Pins | 172 | — |
| Typical Usable Gates | 12,000 | — |
| Number of Logic Elements | 512 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Operating Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt) | — |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI (with external resistor) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Support | Yes (BST/Boundary-Scan Test) | — |
| パッケージ | PQFP-208 (QC208) | 208-pin FineLine BGA-256 |
| 実装タイプ | Surface Mount | — |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Macrocells | — | 512 |
| Usable Gates | — | 1750 |
| User I/Os | — | 208 |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |
| Process Technology | — | EEPROM-based CMOS |