EPM3512AQC208-7 vs EPM3512AQC208-3N 比較
詳細な並列比較: EPM3512AQC208-7 メーカー: Intel および EPM3512AQC208-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 Nrnd仕様比較
| パラメータ | EPM3512AQC208-7 | EPM3512AQC208-3N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $41.72 | $16.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (fCNT) | 116.3 MHz | — |
| User I/Os | 172 | — |
| Logic Elements / LEs | N/A (CPLD macrocell architecture) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Standards Supported | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| パッケージ | 208-Pin PQFP (FQFP, gull-wing) | PQFP-208 |
| 動作温度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Programming | In-System Programmable via JTAG (IEEE Std. 1532) | — |
| Process Technology | CMOS EEPROM, 0.30 um | — |
| RoHS ステータス | Compliant | [DATA_NEEDED: not stated in retrieved snippets] |
| Lead-Free | Yes | — |
| User I/O Pins | — | 172 |
| Logic Array Blocks (LABs) | — | 16 |
| Macrocells per LAB | — | 32 |
| Pin-to-Pin Logic Delay | — | 3 ns (speed grade -3) |
| Global Clock Setup Time | — | [DATA_NEEDED: actual tSU at 3 ns grade] |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) |
| 実装タイプ | — | Surface Mount |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| ISP Compliance | — | IEEE Std. 1532 |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED] |