EPM3512AQC20810 vs EPM3512AQC208-15N 比較
詳細な並列比較: EPM3512AQC20810 メーカー: Altera および EPM3512AQC208-15N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC20810 | EPM3512AQC208-15N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.80 | $20.50 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CPLD (EEPROM-based, non-volatile) | — |
| Macro Cells | 512 | 512 |
| User I/Os | 172 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates (equivalent) | 10000 | — |
| パッケージ | 208-pin PQFP (PQ208) | PQFP-208 (QC208) |
| Speed Grade | -10 (tPD = 10 ns) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 132 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V | 2.5 V / 3.3 V (MultiVolt) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) | Yes (IEEE Std. 1532 compliant) |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 compliant | — |
| Operating Temperature (commercial) | 0 °C to +70 °C | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration Memory | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention | EEPROM (non-volatile) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Maximum User I/O Pins | — | 172 |
| Typical Usable Gates | — | 12,000 |
| Number of Logic Elements | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Operating Supply Voltage (VCCINT) | — | 3.3 V |
| Programmable I/O Standards | — | LVTTL, LVCMOS, PCI (with external resistor) |
| JTAG Support | — | Yes (BST/Boundary-Scan Test) |
| 実装タイプ | — | Surface Mount |
| 動作温度 | — | 0C to +70C (commercial) |