EPM3512AQI208-10N vs EPM3512AFC256-10N 比較
詳細な並列比較: EPM3512AQI208-10N メーカー: Intel および EPM3512AFC256-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQI208-10N | EPM3512AFC256-10N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $12.90 | $43.22 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Family | CMOS EEPROM-based | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 12 | [DATA_NEEDED: number of LABs] |
| User I/Os | 172 (max), 208-pin package | — |
| Propagation Delay (tPD) | 10 ns | — |
| 電源電圧 | 3.3 V | — |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) | — |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) | — |
| Pins | 256 (package), 208 used | — |
| 動作温度 | 0C to 70C | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | — |
| Compliance | RoHS status unknown from data | — |
| Boundary Scan | Built-in BST (IEEE 1149.1) | — |
| Configuration Memory | On-chip EEPROM, non-volatile | — |
| Macrocells | — | 512 |
| Usable Gates | — | 10000 |
| User I/O Pins | — | 208 |
| Operating Frequency (fMAX) | — | [DATA_NEEDED: fMAX MHz] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Setup Time (tSU) | — | 4.5 ns |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 3.3 V or 2.5 V |
| Technology | — | CMOS EEPROM-based, non-volatile |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| パッケージ | — | 256-ball FBGA (17 mm x 17 mm) |
| ISP Interface | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |