EPM3512AQI208-10N vs EPM3512AQI20810 比較
詳細な並列比較: EPM3512AQI208-10N メーカー: Intel および EPM3512AQI20810 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQI208-10N | EPM3512AQI20810 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $12.90 | $21.10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Family | CMOS EEPROM-based | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 12 | 16 (32 macrocells each) |
| User I/Os | 172 (max), 208-pin package | — |
| Propagation Delay (tPD) | 10 ns | — |
| 電源電圧 | 3.3 V | — |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) | — |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) | — |
| Pins | 256 (package), 208 used | — |
| 動作温度 | 0C to 70C | -40 °C to +85 °C (Industrial, "I" suffix) |
| 実装タイプ | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | — |
| Compliance | RoHS status unknown from data | — |
| Boundary Scan | Built-in BST (IEEE 1149.1) | — |
| Configuration Memory | On-chip EEPROM, non-volatile | — |
| Macrocells | — | 512 |
| Usable Gates | — | 10,000 |
| Maximum User I/O Pins | — | 172 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Internal fMAX (logic feedback) | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| MultiVolt I/O Interface | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V compatible |
| パッケージ | — | 208-pin PQFP (PQ208) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| In-System Programmability | — | IEEE Std. 1149.1 JTAG + IEEE Std. 1532 |
| Lead-Free / RoHS | — | Contains lead / RoHS non-compliant (per Altera datasheet marking) |