EPM5032DC-20 vs EPM5032DI-25 比較

詳細な並列比較: EPM5032DC-20 メーカー: Intel および EPM5032DI-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5032DC-20 EPM5032DI-25
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete NRND
在庫状況 In Stock In Stock
単価(USD) $5.05 $18.20
Product Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) UV-erasable Programmable Logic Device (PLD)
Programmable Technology UV-Erasable / OTP EPROM —
Usable Gates 600 —
Macrocells 32 32
Maximum Frequency (fCNT) 71.4 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Supply Voltage (VCC) 5 V —
パッケージ 20-pin DIP (Windowed Ceramic, 0.3" wide) Ceramic DIP, windowed (UV-erasable)
実装タイプ Through-Hole —
Logic Blocks 4 Logic Array Blocks (LABs) —
I/O Pins [DATA_NEEDED: I/O pin count for DIP-20 variant] —
動作温度 [DATA_NEEDED: commercial/industrial/military grade] 0C to +70C (commercial)
RoHS ステータス Compliant (per IC-Components listing) [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Lead Free [DATA_NEEDED: confirmed lead-free] —
Manufacturer Altera (now Intel Programmable Solutions Group) —
Programming Method Altera MAX+PLUS II / Quartus (legacy support) —
Family — MAX 5000
Architecture — PAL-type, CMOS, AND-OR sum-of-products
Product Terms — 320
Logic Gates — [DATA_NEEDED: equivalent gate count]
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Propagation Delay (tPD) — 25 ns
Maximum Clock Frequency (fMAX) — 62.5 MHz
電源電圧 — 5 V
Process Technology — CMOS
ピン数 — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

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