EPM5064JC-1 vs EPM5016DC-20 比較

詳細な並列比較: EPM5064JC-1 メーカー: Altera および EPM5016DC-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5064JC-1 EPM5016DC-20
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND Obsolete
在庫状況 In Stock In Stock
単価(USD) $18.25 $16.50
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) EPLD (UV-Erasable Programmable Logic Device)
Macro Cells 64 —
Usable Gates 1250 (typical) —
Logic Elements 128 (Logic Array Blocks) —
Maximum Operating Frequency 33.3 MHz (fCNT) —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) —
Process Technology 0.8 µm CMOS CMOS, UV-erasable
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] 7
パッケージ 44-pin PLCC (J-lead, windowed ceramic) —
実装タイプ Surface Mount (PLCC socket recommended) —
動作温度 0 °C to +70 °C (commercial, -JC suffix) [DATA_NEEDED: operating temperature range]
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV UV erase + EPROM-style programming via Altera programming hardware
JTAG Boundary Scan Not supported (classic MAX architecture) —
RoHS ステータス Non-compliant (windowed ceramic, contains Pb in glass frit) [DATA_NEEDED: RoHS compliance]
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Macrocells — 16
Product Terms — 160
I/O Pins — 8
Propagation Delay (tPD) — 20 ns
最大クロック周波数 — 62.5 MHz
Maximum Supply Voltage — 5.25 V
Nominal Supply Voltage — 5.0 V
Architecture — PAL-type macrocell with Programmable Interconnect Array (PIA)
Package Type — 20-pin Ceramic DIP (Cerdip) with UV window
Package Suffix Code — DC = Ceramic DIP, Commercial
Speed Grade — -20 = 20 ns tPD

データシート&リソース

すべての製品を閲覧 BOMを作成 見積もり依頼