EPM5064JC-1 vs EPM5128JC 比較

詳細な並列比較: EPM5064JC-1 メーカー: Altera および EPM5128JC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5064JC-1 EPM5128JC
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND Obsolete
在庫状況 In Stock In Stock
単価(USD) $18.25 $9.75
Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) EPLD / CPLD
Macro Cells 64 —
Usable Gates 1250 (typical) —
Logic Elements 128 (Logic Array Blocks) Programmable AND/OR/XOR array
Maximum Operating Frequency 33.3 MHz (fCNT) —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) 5 V (typical)
Process Technology 0.8 µm CMOS CMOS EPROM
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] 8
パッケージ 44-pin PLCC (J-lead, windowed ceramic) —
実装タイプ Surface Mount (PLCC socket recommended) Surface Mount (PLCC socket or solder)
動作温度 0 °C to +70 °C (commercial, -JC suffix) Commercial 0C to +70C
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV —
JTAG Boundary Scan Not supported (classic MAX architecture) —
RoHS ステータス Non-compliant (windowed ceramic, contains Pb in glass frit) [DATA_NEEDED: RoHS status - legacy part]
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Product Family — MAX 5000
Macrocell Count — 128
Propagation Delay (tPD) — 35 ns
ピン数 — 68
Package Type — PLCC-68 (JLCC) ceramic, J-leaded
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Configuration Memory — UV-erasable EPROM (windowed package)
Programming Interface — Altera MAX+PLUS II / A+PLUS / legacy programmer
Boundary Scan — JTAG IEEE 1149.1 (family feature)
Lead-Free — [DATA_NEEDED: lead-free status]

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