EPM5064JC-2 vs EPM5064JC1 比較
詳細な並列比較: EPM5064JC-2 メーカー: Altera および EPM5064JC1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JC-2 | EPM5064JC1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $23.10 | $1.05 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Propagation Delay (tPD) | 45 ns | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Usable Gates | 1250 | 1.25K |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 28 | 28 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Programming Method | UV-erase + EPROM programmer (not ISP) | — |
| パッケージ | 28-pin CLCC (J-lead, ceramic, windowed) | 44-pin PLCC (J-Lead) |
| 動作温度 | [DATA_NEEDED: commercial or industrial grade] | — |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | — |
| Device Type | — | CPLD / EPLD (Erasable PLD) |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| External Clock Input (max) | — | 50 MHz |
| Total Inputs | — | 36 (28 I/O + 7 dedicated + 1 clock) |
| Operating Voltage (VCC) | — | 5 V |
| Program Type | — | EPROM (one-time programmable, UV-erasable) |
| Process Technology | — | CMOS |
| Operating Temperature (JC suffix) | — | 0°C to +70°C (commercial) |
| Supply Current (ICC) | — | [DATA_NEEDED: ICC maximum] |
| RoHS ステータス | — | unknown |
| Lead-Free Status | — | unknown |