EPM5064JI-1 vs EPM5064JC-1 比較

詳細な並列比較: EPM5064JI-1 メーカー: Intel および EPM5064JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5064JI-1 EPM5064JC-1
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND NRND
在庫状況 In Stock In Stock
単価(USD) $3.40 $18.25
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Macrocells 64 —
User I/O Pins [DATA_NEEDED: user I/O count from datasheet] —
パッケージ 68-pin PLCC (windowed ceramic) 44-pin PLCC (J-lead, windowed ceramic)
Logic Elements [DATA_NEEDED: total logic elements] 128 (Logic Array Blocks)
Propagation Delay (tPD) [DATA_NEEDED: combinational tPD from datasheet] —
電源電圧 5 V —
動作温度 [DATA_NEEDED: commercial vs industrial grade temp range] 0 °C to +70 °C (commercial, -JC suffix)
Process Technology CMOS, UV-erasable 0.8 µm CMOS
Speed Grade JI-1 (commercial, -10/-12/-15 family) —
Programmability UV-erasable (windowed package) —
Data Retention 25 years (per MAX 5000 datasheet) —
実装タイプ Surface Mount Surface Mount (PLCC socket recommended)
RoHS ステータス [DATA_NEEDED: not stated in provided data] Non-compliant (windowed ceramic, contains Pb in glass frit)
Macro Cells — 64
Usable Gates — 1250 (typical)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Supply Voltage (VCC) — 5 V nominal (4.75 V – 5.25 V)
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
Dedicated Inputs — [DATA_NEEDED: dedicated input count]
Erasure Method — UV-erasable through quartz window
Programming Method — Altera Logic Programmer + MasterBlaster/ByteBlasterMV
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

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