EPM5128JC-2 vs EPM5130JC-1 比較
詳細な並列比較: EPM5128JC-2 メーカー: Altera および EPM5130JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5128JC-2 | EPM5130JC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.75 | $9.25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | — |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | 19 |
| Propagation Delay (tPD) | 45 ns (max) | 40 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS |
| パッケージ | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | 84-pin PLCC (J-lead) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| 電源電圧 | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| RoHS ステータス | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS compliance] |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 gates |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| I/O Pins | — | 80 |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |